DR. Frank Ertl

Professional


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FOCUS TOPICS

  • Products:

LED driver; step-down converter

DDR1-3 DRAM

  • Technology:

0.35um BCDMOS (SOI)

90-70nm CMOS

 AREAS OF RESPONSIBILITY

  • Projects:

product owner for development and optimization
(to date 6 product families; during validation, qualification, ramp-up and sustaining project phase)

proven project management skills technology-lead product development during high volume production

responsibility to plan, structure and execute product engineering work packages, including prioritization across projects

in charge of achieving project targets and timelines, as well as key performance indicator objectives (esp. quality level)

  • People:

proven leadership experience - direction of an international team of engineers (up to 6 members)

training of new employees; world-wide transfer of knowledge

  • Interfaces:

primary interface to program and quality management (consulting, reporting role)

main contact person for international production sites, design centres and assembly/reliability subcontractors (US, Asia, Europe)

  • Processes:

optimization of the product development business process, revision of the product qualification guidelines, ISO 9001 audits (in each case consulting, supporting function)

Fields of Activities

  • Assembly:

package selection; assembly document preparation and release (package outline, bill of material, bond diagram, marking); control of engineering builds

  • Validation:

functional design analysis (component, wafer); parametric bench characterization (datasheet);
corner behaviour investigation (voltage, temperature, process); development of measurement hard/software and evaluation tools; electrical failure analysis (pico probing, FIB modification); validation result reports

  • Test:

test content definition (FE, BI and BE automated test equipment); implementation and debugging support (hardware, code); determination of screen limits and guard bands; accurate correlation to datasheet; test flows for production; test time reduction; design for test

  • Qualification:

qualification (product, package) according to Jedec JESD47 and AEC Q100; definition of requirements for product stress test; development of HTOL and HAST hardware; electrical and physical failure analysis of qualification fails; implementation of corrective actions; documentation of qualification progress and final report

  • Quality:

root-cause analysis of customer returns and internal monitoring fails; definition of containment and corrective actions on all levels; business process and learning  loop improvements; 8D-reporting to customer

  • Ramp-up:

optimization of yield, test time and quality; periodic statistical investigations (cpk, dpm); handover of released product to supply chain for mass production

TRAININGS

  • Technical:

Advantest:
Memory Test Systems - Applications I+II

Enteq:
IMS/Orion Memory Tester Basic and Advanced Training Course

Prof. Hoffmann:
Design of Analog and Digital CMOS Circuits

Dr. Maichen:
High-Speed Digital Test Techniques

Telefunken:
Production Control Plan and Fundamental Parameters

  • Methodical:

Resultance:
Project Contributor Training Basic Project Management Course

Telefunken:
Failure Mode and Effect Analysis

  • Communication:

Ruth Schaefer:
Cross Cultural Training - China/Taiwan

  • Law:

Global Competence Forum:
Product Risk and Reliability - Worldwide

 


Webmaster: contact@frank-ertl.de

Update: 12/02/20